用于RSFQ位并行处理器的32位无时钟门ALU

IEICE Trans. Electron. Pub Date : 2022-01-01 DOI:10.1587/transele.2021sep0005

T. Kawaguchi, N. Takagi

{"title":"用于RSFQ位并行处理器的32位无时钟门ALU","authors":"T. Kawaguchi, N. Takagi","doi":"10.1587/transele.2021sep0005","DOIUrl":null,"url":null,"abstract":"SUMMARY A 32-bit arithmetic logic unit (ALU) is designed for a rapid single ﬂux quantum (RSFQ) bit-parallel processor. In the ALU, clocked gates are partially replaced by clockless gates. This reduces the number of D ﬂip ﬂops (DFFs) required for path balancing. The number of clocked gates, including DFFs, is reduced by approximately 40 %, and size of the clock distribution network is reduced. The number of pipeline stages becomes modest. The layout design of the ALU and simulation results show the e ﬀ ectiveness of using clockless gates in wide datapath circuits.","PeriodicalId":13259,"journal":{"name":"IEICE Trans. Electron.","volume":"25 1","pages":"245-250"},"PeriodicalIF":0.0000,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor\",\"authors\":\"T. Kawaguchi, N. Takagi\",\"doi\":\"10.1587/transele.2021sep0005\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"SUMMARY A 32-bit arithmetic logic unit (ALU) is designed for a rapid single ﬂux quantum (RSFQ) bit-parallel processor. In the ALU, clocked gates are partially replaced by clockless gates. This reduces the number of D ﬂip ﬂops (DFFs) required for path balancing. The number of clocked gates, including DFFs, is reduced by approximately 40 %, and size of the clock distribution network is reduced. The number of pipeline stages becomes modest. The layout design of the ALU and simulation results show the e ﬀ ectiveness of using clockless gates in wide datapath circuits.\",\"PeriodicalId\":13259,\"journal\":{\"name\":\"IEICE Trans. Electron.\",\"volume\":\"25 1\",\"pages\":\"245-250\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEICE Trans. Electron.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1587/transele.2021sep0005\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEICE Trans. Electron.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1587/transele.2021sep0005","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

摘要为快速单通量量子(RSFQ)位并行处理器设计了一个32位算术逻辑单元(ALU)。在ALU中，时钟门部分被无时钟门取代。这减少了路径平衡所需的D触发器(dff)的数量。时钟门(包括dff)的数量减少了大约40%，时钟分配网络的规模也减小了。管道阶段的数量变得有限。ALU的布置图设计和仿真结果表明了在宽数据路电路中使用无时钟门的有效性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

32-Bit ALU with Clockless Gates for RSFQ Bit-Parallel Processor

SUMMARY A 32-bit arithmetic logic unit (ALU) is designed for a rapid single ﬂux quantum (RSFQ) bit-parallel processor. In the ALU, clocked gates are partially replaced by clockless gates. This reduces the number of D ﬂip ﬂops (DFFs) required for path balancing. The number of clocked gates, including DFFs, is reduced by approximately 40 %, and size of the clock distribution network is reduced. The number of pipeline stages becomes modest. The layout design of the ALU and simulation results show the e ﬀ ectiveness of using clockless gates in wide datapath circuits.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

IEICE Trans. Electron.

自引率

0.00%

发文量