{"title":"一种新的Mosfet栅极氧化物电容校准结构","authors":"Han Xiaojing","doi":"10.1109/CSTIC49141.2020.9282602","DOIUrl":null,"url":null,"abstract":"This paper introduces a new kind of calibration structure for MOSFET gate oxide capacitance. This new calibration structure is used to remove the parasitic interconnect capacitance from the gate oxide capacitor when calculate the gate oxide capacitance. By processing measured data of gate oxide capacitance and this new capacitance calibration structure, we can get the value of gate oxide capacitance more accurately, which provides a more accurate guarantee for SPICE model and circuit design.","PeriodicalId":6848,"journal":{"name":"2020 China Semiconductor Technology International Conference (CSTIC)","volume":"22 1","pages":"1-3"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"One New Calibration Structure of Mosfet Gate Oxide Capacitor\",\"authors\":\"Han Xiaojing\",\"doi\":\"10.1109/CSTIC49141.2020.9282602\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper introduces a new kind of calibration structure for MOSFET gate oxide capacitance. This new calibration structure is used to remove the parasitic interconnect capacitance from the gate oxide capacitor when calculate the gate oxide capacitance. By processing measured data of gate oxide capacitance and this new capacitance calibration structure, we can get the value of gate oxide capacitance more accurately, which provides a more accurate guarantee for SPICE model and circuit design.\",\"PeriodicalId\":6848,\"journal\":{\"name\":\"2020 China Semiconductor Technology International Conference (CSTIC)\",\"volume\":\"22 1\",\"pages\":\"1-3\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 China Semiconductor Technology International Conference (CSTIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSTIC49141.2020.9282602\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 China Semiconductor Technology International Conference (CSTIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSTIC49141.2020.9282602","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
One New Calibration Structure of Mosfet Gate Oxide Capacitor
This paper introduces a new kind of calibration structure for MOSFET gate oxide capacitance. This new calibration structure is used to remove the parasitic interconnect capacitance from the gate oxide capacitor when calculate the gate oxide capacitance. By processing measured data of gate oxide capacitance and this new capacitance calibration structure, we can get the value of gate oxide capacitance more accurately, which provides a more accurate guarantee for SPICE model and circuit design.