A Low-Phase-Noise 20 GHz Phase-Locked Loop with Parasitic Capacitance Reduction Technique for V-band Applications

A power efficient 20 GHz PLL for 60 GHz transceiver is presented in this paper. The proposed PLL consists of low phase noise voltage controlled oscillator, low power consumption divider chain, phase frequency detector, charge pump, and loop filter. The PLL covers frequency from 19.43 GHz to 20.62 GHz with 2-bit switched capacitor banks. Implemented in 65 nm CMOS technology, the fully integrated PLL occupies an area of 1.3mm2. A phase noise of PLL is −102.05 dBc/Hz at 1 MHz offset frequency and a figure of merit of −174.35 dBc/Hz with 23.6 mW power consumnption.