Gerardo Marcos Tornez-Xavier, L. M. Flores-Nava, F. Gómez-Castañeda, J. Moreno-Cadenas
{"title":"赋值任务的记忆优化器","authors":"Gerardo Marcos Tornez-Xavier, L. M. Flores-Nava, F. Gómez-Castañeda, J. Moreno-Cadenas","doi":"10.1109/ICEEE.2018.8533979","DOIUrl":null,"url":null,"abstract":"This work shows an analog CMOS matrix compatible with memristors, where they work as dynamic resistors. They are also programmed to initial state values according to one assignment optimization task, taken here as an application vehicle. The whole matrix accomplishes a parallel competitive computation, where a winner-take-all mechanism is inherent by architecture. The expected complexity due to area in silicon of this memristive circuit and its connectivity are moderate, as is evident from observing its electrical diagram. Also, its performance is acceptable as proven via SPICE simulations, using 0.5-micron CMOS process. Lower processing time might be possible with latest CMOS technologies.","PeriodicalId":6924,"journal":{"name":"2018 15th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)","volume":"16 1","pages":"1-5"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Memristive Optimizer for the Assignment Task\",\"authors\":\"Gerardo Marcos Tornez-Xavier, L. M. Flores-Nava, F. Gómez-Castañeda, J. Moreno-Cadenas\",\"doi\":\"10.1109/ICEEE.2018.8533979\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work shows an analog CMOS matrix compatible with memristors, where they work as dynamic resistors. They are also programmed to initial state values according to one assignment optimization task, taken here as an application vehicle. The whole matrix accomplishes a parallel competitive computation, where a winner-take-all mechanism is inherent by architecture. The expected complexity due to area in silicon of this memristive circuit and its connectivity are moderate, as is evident from observing its electrical diagram. Also, its performance is acceptable as proven via SPICE simulations, using 0.5-micron CMOS process. Lower processing time might be possible with latest CMOS technologies.\",\"PeriodicalId\":6924,\"journal\":{\"name\":\"2018 15th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)\",\"volume\":\"16 1\",\"pages\":\"1-5\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 15th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEEE.2018.8533979\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 15th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEEE.2018.8533979","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This work shows an analog CMOS matrix compatible with memristors, where they work as dynamic resistors. They are also programmed to initial state values according to one assignment optimization task, taken here as an application vehicle. The whole matrix accomplishes a parallel competitive computation, where a winner-take-all mechanism is inherent by architecture. The expected complexity due to area in silicon of this memristive circuit and its connectivity are moderate, as is evident from observing its electrical diagram. Also, its performance is acceptable as proven via SPICE simulations, using 0.5-micron CMOS process. Lower processing time might be possible with latest CMOS technologies.