{"title":"非理想栅极结构纳米线场效应管的实用化研究","authors":"Jyi-Tsong Lin, Chun-Yu Chen, M. Chiang","doi":"10.1109/SNW.2010.5562568","DOIUrl":null,"url":null,"abstract":"Device characteristics of the nanowire FETs with nonideal gate structures, such as nonuniform gate oxide and elliptic wire, are investigated using 3D numerical simulation. As the nonideal nanowire cases show acceptable device characteristics and still maintain good performance projection, various nanowires FETs are thus flexible for manufacturing. By simply changing the wire diameter from 10 nm to 7 nm at the 25 nm technology node, 22% improvement in gate delay is predicted.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"116 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Pragmatic study of the nanowire FETs with nonideal gate structures\",\"authors\":\"Jyi-Tsong Lin, Chun-Yu Chen, M. Chiang\",\"doi\":\"10.1109/SNW.2010.5562568\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Device characteristics of the nanowire FETs with nonideal gate structures, such as nonuniform gate oxide and elliptic wire, are investigated using 3D numerical simulation. As the nonideal nanowire cases show acceptable device characteristics and still maintain good performance projection, various nanowires FETs are thus flexible for manufacturing. By simply changing the wire diameter from 10 nm to 7 nm at the 25 nm technology node, 22% improvement in gate delay is predicted.\",\"PeriodicalId\":6433,\"journal\":{\"name\":\"2010 Silicon Nanoelectronics Workshop\",\"volume\":\"116 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 Silicon Nanoelectronics Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SNW.2010.5562568\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Silicon Nanoelectronics Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SNW.2010.5562568","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Pragmatic study of the nanowire FETs with nonideal gate structures
Device characteristics of the nanowire FETs with nonideal gate structures, such as nonuniform gate oxide and elliptic wire, are investigated using 3D numerical simulation. As the nonideal nanowire cases show acceptable device characteristics and still maintain good performance projection, various nanowires FETs are thus flexible for manufacturing. By simply changing the wire diameter from 10 nm to 7 nm at the 25 nm technology node, 22% improvement in gate delay is predicted.
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