Analysis and design of low power, high speed comparators in 180nm technology with low supply voltages for ADCs

This paper presents the analysis of different types of comparator and their simulated results as the requirement for low-power, high speed analog to digital converters (ADCs)is increasing, this drive towards the CMOS comparators which are capable to work in Low supply voltage at maximum speed with high power efficiency. Simulation is done by Cadence Virtuoso Analog Design Environment using SCL 180nm technology and simulation done at 1.2 Volt supply voltage. The comparator has least power consumption of 96.5pw with a delay of 0.56ns. During this the clock frequency was 250 MHz Also authors have analyzed DC responses and transient responses.