Low energy asynchronous adders

Asynchronous circuits are often presented as a means to achieve low power operation. We investigate their suitability for low energy applications, where long battery life and delay tolerance is the principal design goal, and where performance is not a critical requirement. Three adder circuits are studied -two dynamic and one based on pass-transistor logic. All adders combine dual-rail and bundled-data circuits. The circuits are simulated at a wide supply-voltage range, down to their minimal operating point. Leakage energy (at 0.18 /spl mu/m) is found to be negligible. Transistor count is found to be an unreliable predictor of energy dissipation. Keepers in dynamic logic are eliminated when possible. The least amount of energy is dissipated by a modified version of a two-bit dynamic adder originally proposed by K.S. Chong et al. (see Int. Symp. Circuits and Systems, 2002).