Ahmed S. H. Ahmed, A. Simsek, A. Farid, A. Carter, M. Urteaga, M. Rodwell
{"title":"采用异构集成的InP HBT和Si CMOS技术,实现了输出功率为16dBm的w波段发射通道和直流功耗为58.6mW的接收通道","authors":"Ahmed S. H. Ahmed, A. Simsek, A. Farid, A. Carter, M. Urteaga, M. Rodwell","doi":"10.1109/mwsym.2019.8701000","DOIUrl":null,"url":null,"abstract":"We report a high output power transmitter and a low DC power receiver front-end channels of a phased array transceiver, designed in heterogeneously integrated 250 nm InP HBT and 130 nm Si CMOS technologies. The transmitter channel consists of a variable gain amplifier, an IQ-vector-modulator-based phase shifter, and a power amplifier. External Analog control signals are used to adjust the phase shifter and VGA states. The transmitter has a saturated output power of 16dBm at 90GHz while consuming 885mW DC power. The receiver channel uses a low noise amplifier with a similar phase shifter, and a variable gain amplifier. 4-bit DACs are implemented in the CMOS to control the phase shifter and VGA. The overall the receiver channel has ~26dB small signal gain at 58.6 mW DC power dissipation. The areas of the transmitter and receiver channels are 2.7x0.81mm2 and 2.1x0.76mm2 respectively.","PeriodicalId":6720,"journal":{"name":"2019 IEEE MTT-S International Microwave Symposium (IMS)","volume":"106 1","pages":"654-657"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A W-Band transmitter channel with 16dBm output power and a receiver channel with 58.6mW DC power consumption using heterogeneously integrated InP HBT and Si CMOS technologies\",\"authors\":\"Ahmed S. H. Ahmed, A. Simsek, A. Farid, A. Carter, M. Urteaga, M. Rodwell\",\"doi\":\"10.1109/mwsym.2019.8701000\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We report a high output power transmitter and a low DC power receiver front-end channels of a phased array transceiver, designed in heterogeneously integrated 250 nm InP HBT and 130 nm Si CMOS technologies. The transmitter channel consists of a variable gain amplifier, an IQ-vector-modulator-based phase shifter, and a power amplifier. External Analog control signals are used to adjust the phase shifter and VGA states. The transmitter has a saturated output power of 16dBm at 90GHz while consuming 885mW DC power. The receiver channel uses a low noise amplifier with a similar phase shifter, and a variable gain amplifier. 4-bit DACs are implemented in the CMOS to control the phase shifter and VGA. The overall the receiver channel has ~26dB small signal gain at 58.6 mW DC power dissipation. The areas of the transmitter and receiver channels are 2.7x0.81mm2 and 2.1x0.76mm2 respectively.\",\"PeriodicalId\":6720,\"journal\":{\"name\":\"2019 IEEE MTT-S International Microwave Symposium (IMS)\",\"volume\":\"106 1\",\"pages\":\"654-657\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE MTT-S International Microwave Symposium (IMS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/mwsym.2019.8701000\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE MTT-S International Microwave Symposium (IMS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/mwsym.2019.8701000","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A W-Band transmitter channel with 16dBm output power and a receiver channel with 58.6mW DC power consumption using heterogeneously integrated InP HBT and Si CMOS technologies
We report a high output power transmitter and a low DC power receiver front-end channels of a phased array transceiver, designed in heterogeneously integrated 250 nm InP HBT and 130 nm Si CMOS technologies. The transmitter channel consists of a variable gain amplifier, an IQ-vector-modulator-based phase shifter, and a power amplifier. External Analog control signals are used to adjust the phase shifter and VGA states. The transmitter has a saturated output power of 16dBm at 90GHz while consuming 885mW DC power. The receiver channel uses a low noise amplifier with a similar phase shifter, and a variable gain amplifier. 4-bit DACs are implemented in the CMOS to control the phase shifter and VGA. The overall the receiver channel has ~26dB small signal gain at 58.6 mW DC power dissipation. The areas of the transmitter and receiver channels are 2.7x0.81mm2 and 2.1x0.76mm2 respectively.