5.5 V容限I/O在2.5 V 0.25 /spl μ m CMOS技术

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-24 DOI:10.1109/CICC.2000.852698

A. Annema, G. Geelen, P. C. D. Jong

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引用次数: 3

摘要

在2.5 V 0.25 /spl mu/m CMOS技术中，展示了5.5 V耐受开漏I/O，该I/O不需要工艺选项。电路技术限制了氧化应力和热载流子退化，导致5.5 V焊盘电压摆幅，2.2 V电源电压，10 MHz开关频率的外推寿命为数百年。所示的概念也可以在其他类型的I/O中实现，并且可以很容易地扩展到新的进程。

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5.5 V tolerant I/O in a 2.5 V 0.25 /spl mu/m CMOS technology

Robust high-voltage tolerant I/O that does not need process options is presented, demonstrated on 5.5 V tolerant open-drain I/O in a 2.5 V 0.25 /spl mu/m CMOS technology. Circuit techniques limit oxide stress and hot-carrier degradation, resulting in hundreds of years extrapolated lifetime for 5.5 V pad voltage swing, 2.2 V supply voltage, 10 MHz switching frequency. The shown concepts are also implemented in other types of I/O and can easily be scaled towards newer processes.

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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