Session 7 overview: Neuromorphic, clocking and security circuits: Digital circuits subcommittee

The eight papers in this session highlight developments in neuromorphic acceleration, clocking circuits and security building blocks. A highlighted paper demonstrates a neuromorphic accelerator with stochastic synapses and embedded online reinforcement learning in autonomous micro-robots. The clocking papers presented demonstrate an all-digital multiplying DLL, a synthesizable fractional-N PLL and a synthesizable period-jitter sensor. Improvements to random-number generators and physically unclonable functions provide lower error rates and lossless stabilization by a novel remapping scheme.