Efficient power analysis of combinational circuits

Designers of low power chips are finding it increasingly useful to obtain estimates of average power consumption early in the design phase. They need a fast power estimation capability which gives reasonably accurate power estimates. In this paper, we present some ideas to obtain an efficient implementation of probabilistic power analysis for combinational circuits. These ideas are based on the observation that in order to obtain a fast implementation, it is very important to control the sizes of the Reduced Ordered Binary Decision Diagrams (ROBDDs) that are created during analysis. However, controlling sizes of ROBDDs could impact the accuracy of the result. We explore the consequences of making the trade-off between performance of the implementation and accuracy. Our experimental results illustrate that our implementation can provide estimates that are within 5% of a commonly used probabilistic method and runs 10 times faster, on average. Our method also scales very well for large circuits.