A Novel 10-bit 1.2GS/s Hybrid Digital to Analog Converter with 8.4mW Power Consumption

In this paper, a novel 10-bit 1.2 GS/s hybrid digital to analog converter (DAC) is presented. In this work, a resistor ladder beside the unit current sources is employed to implement the higher value bits. Using a resistor ladder for scaling the current sources causes to decrease the number of current sources impressively. In addition, the complicated decoder circuits used in segmented structures are replaced by simple digital logics with fewer transistors. simulation results in 65 nm CMOS technology demonstrate that the proposed DAC consumes only 8.4 mW power with a 1.2 V power supply, which is an improvement in comparison with recent works. Moreover, simulation results show that the INL and DNL are less than 0.25 and 0.12 LSB, respectively. Also, more than 74 dB SFDR is obtained in the entire 600 MHz Nyquist bandwidth.