{"title":"一种减少抖动特性的新型电荷泵锁相环","authors":"Myoung-Su Lee, T. Cheung, W. Choi","doi":"10.1109/ICVC.1999.821010","DOIUrl":null,"url":null,"abstract":"A new charge pump structure is proposed that can improve jitter characteristics of a Phase-Locked Loop (PLL) by blocking the control voltage leakages. The new structure also has low power consumption because it uses a self-biased method that switches the current flow only on demand. A PLL with the proposed charge pump is designed with 0.6 /spl mu/m CMOS process technology and evaluated by post-layout simulation.","PeriodicalId":13415,"journal":{"name":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","volume":"44 1","pages":"596-598"},"PeriodicalIF":0.0000,"publicationDate":"1999-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"A novel charge pump PLL with reduced jitter characteristics\",\"authors\":\"Myoung-Su Lee, T. Cheung, W. Choi\",\"doi\":\"10.1109/ICVC.1999.821010\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new charge pump structure is proposed that can improve jitter characteristics of a Phase-Locked Loop (PLL) by blocking the control voltage leakages. The new structure also has low power consumption because it uses a self-biased method that switches the current flow only on demand. A PLL with the proposed charge pump is designed with 0.6 /spl mu/m CMOS process technology and evaluated by post-layout simulation.\",\"PeriodicalId\":13415,\"journal\":{\"name\":\"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)\",\"volume\":\"44 1\",\"pages\":\"596-598\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-10-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICVC.1999.821010\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVC.1999.821010","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel charge pump PLL with reduced jitter characteristics
A new charge pump structure is proposed that can improve jitter characteristics of a Phase-Locked Loop (PLL) by blocking the control voltage leakages. The new structure also has low power consumption because it uses a self-biased method that switches the current flow only on demand. A PLL with the proposed charge pump is designed with 0.6 /spl mu/m CMOS process technology and evaluated by post-layout simulation.
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