一个900兆赫,2.5毫安CMOS频率合成器与自动SC调谐回路

Tsung-Hsien Lin, W. Kaiser
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引用次数: 138

摘要

为WINS(无线集成网络传感器)应用开发了一种以0.6 /spl mu/m CMOS技术实现的900 MHz锁相环频率合成器。它集成了一个自动SC离散调谐回路,将频率调谐范围扩展到20%,而CMOS变容管连续调谐的VCO增益保持在仅20 MHz/V的低水平,以最小化参考杂散。该频率合成器在100 kHz偏移时实现-102 dBc/Hz的相位噪声,参考杂散低于-55 dBc。合成器,包括片上压控振荡器,从3v电源仅耗散2.5 mA。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 900 MHz, 2.5 mA CMOS frequency synthesizer with an automatic SC tuning loop
A 900 MHz PLL frequency synthesizer implemented in 0.6 /spl mu/m CMOS technology is developed for WINS (Wireless Integrated Network Sensors) applications. It incorporates an automatic SC discrete-tuning loop to extend the frequency tuning range to 20% while the VCO gain from the CMOS varactor continuous-tuning is kept low at only 20 MHz/V, to minimize the reference spurs. This frequency synthesizer achieves a phase noise of -102 dBc/Hz at 100 kHz offset and reference spurs below -55 dBc. The synthesizer, including an on-chip VCO, dissipates only 2.5 mA from a 3 V supply.
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