具有非重叠结构和凹槽通道的1T DRAM单元的研究

2010 Silicon Nanoelectronics Workshop Pub Date : 2010-06-13 DOI:10.1109/SNW.2010.5562554

Sang Wan Kim, Garam Kim, Wonjoo Kim, Hyoungsoo Ko, Byung-Gook Park

{"title":"具有非重叠结构和凹槽通道的1T DRAM单元的研究","authors":"Sang Wan Kim, Garam Kim, Wonjoo Kim, Hyoungsoo Ko, Byung-Gook Park","doi":"10.1109/SNW.2010.5562554","DOIUrl":null,"url":null,"abstract":"In this paper, a capacitor-less 1T DRAM cell transistor with non-overlap structure and recessed channel is presented. Because of the non-overlap structure between gate and source/drain, GIDL (Gate Induced Drain Leakage) current is efficiently suppressed at hold condition. This results in more than 1 s retention time at 25 °C and 100 ms at 85 °C","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"36 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Investigation of 1T DRAM cell with non-overlap structure and recessed channel\",\"authors\":\"Sang Wan Kim, Garam Kim, Wonjoo Kim, Hyoungsoo Ko, Byung-Gook Park\",\"doi\":\"10.1109/SNW.2010.5562554\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a capacitor-less 1T DRAM cell transistor with non-overlap structure and recessed channel is presented. Because of the non-overlap structure between gate and source/drain, GIDL (Gate Induced Drain Leakage) current is efficiently suppressed at hold condition. This results in more than 1 s retention time at 25 °C and 100 ms at 85 °C\",\"PeriodicalId\":6433,\"journal\":{\"name\":\"2010 Silicon Nanoelectronics Workshop\",\"volume\":\"36 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 Silicon Nanoelectronics Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SNW.2010.5562554\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Silicon Nanoelectronics Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SNW.2010.5562554","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

本文提出了一种无重叠结构、凹槽沟道的无电容1T DRAM单元晶体管。由于栅极和源漏之间的非重叠结构，在保持状态下可以有效地抑制栅极感应漏电流。这导致在25°C下保持时间超过1 s，在85°C下保持时间超过100 ms

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Investigation of 1T DRAM cell with non-overlap structure and recessed channel

In this paper, a capacitor-less 1T DRAM cell transistor with non-overlap structure and recessed channel is presented. Because of the non-overlap structure between gate and source/drain, GIDL (Gate Induced Drain Leakage) current is efficiently suppressed at hold condition. This results in more than 1 s retention time at 25 °C and 100 ms at 85 °C

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2010 Silicon Nanoelectronics Workshop

自引率

0.00%

发文量