超大规模集成电路设计初期的良率损失预测

Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference Pub Date : 1996-05-05 DOI:10.1109/CICC.1996.510505

H. Heineken, J. Khare, Wojciech Maly

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引用次数: 27

摘要

本文介绍了三种新的产量模型。第一种方法将布局的关键区域作为输入;第二种方法以金属线之间的最小间距近似临界区域;第三种是使用晶体管密度来模拟临界区域。利用制造数据对模型进行了开发和验证。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Yield loss forecasting in the early phases of the VLSI design process

This paper describes three new yield models. The first takes as input the critical area of a layout; the second approximates the critical area with the minimum spacing area between metal lines; and the third uses transistor density to model critical area. The models were developed and verified using manufacturing data.

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来源期刊

Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference

CiteScore

3.80

自引率

0.00%

发文量