Yifu Huang, Xiaohan Wu, Yuqian Gu, Ruijing Ge, Jiahan Zhang, Yao‐Feng Chang, D. Akinwande, Jack C. Lee
{"title":"神经形态计算的二维RRAM和Verilog-A模型","authors":"Yifu Huang, Xiaohan Wu, Yuqian Gu, Ruijing Ge, Jiahan Zhang, Yao‐Feng Chang, D. Akinwande, Jack C. Lee","doi":"10.1109/NMDC50713.2021.9677559","DOIUrl":null,"url":null,"abstract":"Resistive random-access memory (RRAM) has become one of the most promising devices for emerging non-volatile memory and brain-inspired neuromorphic computing applications. As a two-dimensional material, monolayer rhenium diselenide (ReSe2) has been reported to exhibit non-volatile resistive switching (NVRS) phenomenon and applied in RRAM devices. In this work, a ReSe2-based RRAM device is proposed. Multi-step resistive switching behavior is observed under DC sweep. By applying proper pulse stimulus, it has been demonstrated that the proposed device exhibits long-term potentiation and depression (LTP/LTD), which is implemented in a Verilog-A model for the purpose of circuit-level simulation.","PeriodicalId":6742,"journal":{"name":"2021 IEEE 16th Nanotechnology Materials and Devices Conference (NMDC)","volume":"26 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2021-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"2D RRAM and Verilog-A model for Neuromorphic Computing\",\"authors\":\"Yifu Huang, Xiaohan Wu, Yuqian Gu, Ruijing Ge, Jiahan Zhang, Yao‐Feng Chang, D. Akinwande, Jack C. Lee\",\"doi\":\"10.1109/NMDC50713.2021.9677559\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Resistive random-access memory (RRAM) has become one of the most promising devices for emerging non-volatile memory and brain-inspired neuromorphic computing applications. As a two-dimensional material, monolayer rhenium diselenide (ReSe2) has been reported to exhibit non-volatile resistive switching (NVRS) phenomenon and applied in RRAM devices. In this work, a ReSe2-based RRAM device is proposed. Multi-step resistive switching behavior is observed under DC sweep. By applying proper pulse stimulus, it has been demonstrated that the proposed device exhibits long-term potentiation and depression (LTP/LTD), which is implemented in a Verilog-A model for the purpose of circuit-level simulation.\",\"PeriodicalId\":6742,\"journal\":{\"name\":\"2021 IEEE 16th Nanotechnology Materials and Devices Conference (NMDC)\",\"volume\":\"26 1\",\"pages\":\"1-4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-12-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE 16th Nanotechnology Materials and Devices Conference (NMDC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NMDC50713.2021.9677559\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 16th Nanotechnology Materials and Devices Conference (NMDC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NMDC50713.2021.9677559","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
2D RRAM and Verilog-A model for Neuromorphic Computing
Resistive random-access memory (RRAM) has become one of the most promising devices for emerging non-volatile memory and brain-inspired neuromorphic computing applications. As a two-dimensional material, monolayer rhenium diselenide (ReSe2) has been reported to exhibit non-volatile resistive switching (NVRS) phenomenon and applied in RRAM devices. In this work, a ReSe2-based RRAM device is proposed. Multi-step resistive switching behavior is observed under DC sweep. By applying proper pulse stimulus, it has been demonstrated that the proposed device exhibits long-term potentiation and depression (LTP/LTD), which is implemented in a Verilog-A model for the purpose of circuit-level simulation.