基于三维集成电路的低功耗立体匹配处理器的设计与分析

Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07) Pub Date : 2013-09-04 DOI:10.1109/ISLPED.2013.6629260

Seung-Ho Ok, Kyeong-Ryeol Bae, S. Lim, Byungin Moon

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引用次数: 6

摘要

本文给出了基于三维集成电路的低功耗立体匹配处理器的综合设计与分析结果。我们的设计工作范围从架构设计和验证到基于GlobalFoundries 130-nm PDK的RTL-to-GDSII设计和签署分析。我们对3D IC设计与2D IC设计相比的面积、性能和功耗优势进行了全面的研究。与2D IC设计相比，我们的2层3D IC设计实现了43%的面积，14%的线长和13%的功耗节约。我们还研究了一种基于管道的分区方法，该方法在平衡每个层的大小的同时，有效地减少了功耗和tsv的总数。

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Design and analysis of 3D IC-based low power stereo matching processors

This paper presents comprehensive design and analysis results of 3D IC-based low-power stereo matching processors. Our design efforts range from architecture design and verification to RTL-to-GDSII design and sign-off analysis based on GlobalFoundries 130-nm PDK. We conduct comprehensive studies on the area, performance, and power benefits of our 3D IC designs over 2D IC designs. Our 2-tier 3D IC designs attain 43% area, 14% wire length, and 13% power saving over 2D IC designs. We also study a pipeline-based partitioning method shown to be effective at minimizing power consumption and the total number of TSVs while balancing the size of each tier.

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Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07)

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