126mW 56Gb/s NRZ有线收发器,用于16nm FinFET的同步短距离应用

Marc Erett, D. Carey, James Hudner, R. Casey, Kevin Geary, Pedro Neto, M. Raj, S. McLeod, Hongtao Zhang, A. Roldan, Hongyuan Zhao, P. Chiang, Haibing Zhao, Kee Hian Tan, Y. Frans, Ken Chang
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引用次数: 19

摘要

业界最近提出了同步高速接口标准,目标是通过非常短的PCB走线进行芯片对芯片通信[1]。图16.7.1显示了这样一个接口的示例。8个56Gb/s的NRZ通道,每个方向的总带宽为448Gb/s。信道插入损耗和传播延迟因信道而异,从BGA到BGA的28GHz最大插入损耗为8dB。两个封装内部的路由在28GHz时增加了额外的3dB插入损耗。利用相对较低的信道损耗,该接口有望采用简单的低功耗发送/接收电路。然而,由于车道间的传播延迟变化,仍然需要采用单车道倾斜方案。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET
The industry has recently proposed standards for synchronous high-speed interfaces targeting chip-to-chip communication across a very short PCB trace [1]. Figure 16.7.1 shows an example of such an interface. Eight 56Gb/s NRZ lanes provide a total of 448Gb/s aggregate bandwidth in each direction. The channel insertion loss and propagation delay varies from lane to lane, with a maximum insertion loss of 8dB at 28GHz from BGA to BGA. The routing inside the two packages adds an additional 3dB insertion loss at 28GHz. Taking advantage of the relatively low channel loss, the interface is expected to adopt simple transmitter/receiver circuits with low power consumption. However, a per-lane deskewing scheme is still required due to the propagation delay variations between lanes.
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