{"title":"Π-gate纳米线TANOS多晶硅TFT非易失性存储器","authors":"Min-Feng Hung, Jiang-Hung Chen, Yung-Chun Wu","doi":"10.1109/SNW.2010.5562547","DOIUrl":null,"url":null,"abstract":"This work we demonstrate a TANOS nonvolatile memory (NVM) with poly-Si nanowire (NW) channels and Pi-gate (Π-gate) structure. Π-gate structure in this TANOS NVM increase on current (I<inf>on</inf>), decrease threshold voltage (V<inf>th</inf>) and subthreshold slope (SS), and enlarge the memory window (ΔV<inf>th</inf>). This NVM device behaves fast program/erase (P/E) speed; 3 V memory window can be achieved by applying 18 V in 10 µs. The 70 % of initial memory window has been maintained after 10<sup>4</sup> P/E-cycle stress.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Π-gate nanowires TANOS poly-Si TFT nonvolatile memory\",\"authors\":\"Min-Feng Hung, Jiang-Hung Chen, Yung-Chun Wu\",\"doi\":\"10.1109/SNW.2010.5562547\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work we demonstrate a TANOS nonvolatile memory (NVM) with poly-Si nanowire (NW) channels and Pi-gate (Π-gate) structure. Π-gate structure in this TANOS NVM increase on current (I<inf>on</inf>), decrease threshold voltage (V<inf>th</inf>) and subthreshold slope (SS), and enlarge the memory window (ΔV<inf>th</inf>). This NVM device behaves fast program/erase (P/E) speed; 3 V memory window can be achieved by applying 18 V in 10 µs. The 70 % of initial memory window has been maintained after 10<sup>4</sup> P/E-cycle stress.\",\"PeriodicalId\":6433,\"journal\":{\"name\":\"2010 Silicon Nanoelectronics Workshop\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 Silicon Nanoelectronics Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SNW.2010.5562547\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Silicon Nanoelectronics Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SNW.2010.5562547","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This work we demonstrate a TANOS nonvolatile memory (NVM) with poly-Si nanowire (NW) channels and Pi-gate (Π-gate) structure. Π-gate structure in this TANOS NVM increase on current (Ion), decrease threshold voltage (Vth) and subthreshold slope (SS), and enlarge the memory window (ΔVth). This NVM device behaves fast program/erase (P/E) speed; 3 V memory window can be achieved by applying 18 V in 10 µs. The 70 % of initial memory window has been maintained after 104 P/E-cycle stress.
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