通过顺序敏感临界区检测非竞争并发性错误

Ruirui C. Huang, Erik Halberg, G. Suh
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引用次数: 8

摘要

本文引入了一种新的非竞争并发错误的启发式条件——顺序敏感临界区,并提出了一种基于该条件的运行时错误检测方案。顺序敏感的临界区被定义为一对临界区,根据它们执行的顺序,它们可能导致不确定的共享内存状态。从某种意义上说,顺序敏感临界区可以看作是将数据竞争作为捕获非竞争错误的潜在错误条件的直觉的扩展。实验表明,该方案对多种类型的非种族错误有很好的覆盖,误报较少。例如,该方案检测了被测试的所有9个真实世界的非种族bug以及超过90%的注入的非种族bug。此外,本文还提出了一种高效的硬件架构,该架构支持所提出的方案,只需进行少量硬件更改和少量额外状态-每个核心9 kb缓冲区和每个数据缓存块1位标签。基于硬件的方案仍然可以检测到所测试的所有9个真实世界的错误,以及超过84%的注入的非种族错误。此外,硬件支持的方案对性能的影响可以忽略不计,平均降低0.23%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Non-race concurrency bug detection through order-sensitive critical sections
This paper introduces a new heuristic condition for non-race concurrency bugs, named order-sensitive critical sections, and proposes a run-time bug detection scheme based on the condition. The order-sensitive critical sections are defined as a pair of critical sections that can lead to non-deterministic shared memory state depending on the order in which they execute. In a sense, the order-sensitive critical sections can be seen as extending the intuition in using data races as a potential bug condition to capture non-race bugs. Experiments show that the proposed scheme provides a good coverage for multiple types of non-race bugs, with a small number of false positives. For example, the scheme detected all 9 real-world non-race bugs that were tested as well as over 90% of injected non-race bugs. Additionally, this paper presents an efficient hardware architecture that supports the proposed scheme with minor hardware changes and a small amount of additional state - a 9-KB buffer per core and a 1-bit tag per data cache block. The hardware-based scheme could still detect all 9 real-world bugs that were tested and more than 84% of the injected non-race bugs. Moreover, the hardware supported scheme has a negligible impact on performance, with a 0.23% slowdown on average.
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