An FPGA/SoC Approach to On-Board Data Processing Enabling New Mars Science with Smart Payloads

A proposed Mars Scout Mission known as MARVEL is vying for the 2011 launch opportunity. One of its primary instruments, MATMOS, will produce large volumes of data in short, 3-minute bursts during its on-orbit observation of sunrise and sunset. The remaining orbit time of 112 minutes is available for on-board data processing to reduce data volume prior to downlink. This data processing relies heavily on floating-point FFTs. The Xilinx Virtex-II Pro FPGA was evaluated in a previous research task, but could not meet the performance requirements, even with an integrated soft-core floating-point unit (FPU). The next-generation Virtex-4 FPGA contains an auxiliary processor unit (APU) that provides a flexible high bandwidth interface for fabric co-processor modules (FCM) to the PowerPC405 core. In this paper we show that coupling the FPU FCM with the APU provides sufficient computation power to meet MATMOS's data processing requirements when implemented in a multi-processor, dual-FPGA system.