A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer

Complex SoCs in nanoscale CMOS integrate a variety of digital compute/memory and analog/mixed-signal circuits such as SerDes transceivers, RF/wireless front-end, PLLs, sensors, etc. On-chip low-dropout regulators (LDOs) isolate the input $\mathrm{V}_{\text{in}}$ noise from switching DC-DC converters powering the digital blocks (Fig. 30.4.1) and provide high power-supply rejection (PSR) to the noise-sensitive analog/mixed-signal circuits by modulating the small-signal output resistance $(\mathrm{R}_{0}$) of the power FET in the saturation region. Therefore, the minimum dropout (DO) voltage must be larger than the necessary gate overdrive (OV). While larger DO enables higher Ro and better PSR, it degrades the LDO power conversion efficiency (PCE). Using larger power FETs can reduce OV and DO for a target $\mathrm{l}_{\max}$ but at the cost of more die area. Therefore, LDO designs that provide the required high PSR while maximizing PCE and area efficiency are essential for high-performance SoCs [1].