{"title":"一种用于便携式脑电图采集的0.5 v多通道低噪声读出前端。","authors":"Wen-Yen Huang, Yu-Wei Cheng, Kea-Tiong Tang","doi":"10.1109/EMBC.2015.7318492","DOIUrl":null,"url":null,"abstract":"This article presents a low-noise readout front-end suitable for Electroencephalogram (EEG) acquisition. The chip includes 8-channel fully-differential instrumentation amplifiers, utilizing chopper stabilization technique for reducing the flicker noise, each amplifier with a small Gm-C low-pass filter, a programmable gain amplifier, and a 10-bit successive approximation register (SAR) ADC with a detect logic for DAC switching. The chip is fabricated with the TSMC 90nm CMOS process. The low-noise readout front-end has simulated frequency response from 0.57 Hz to 213 Hz, programmable gain from 54.4 dB to 87.6 dB, integrated input-referred noise of 0.358 μVrms within EEG bandwidth, a noise efficiency factor (NEF) of 2.43, and a power efficiency factor (PEF) of 2.95. The overall system consumes 32.08 μW under 0.5-V supply.","PeriodicalId":72689,"journal":{"name":"Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference","volume":"40 1","pages":"837-40"},"PeriodicalIF":0.0000,"publicationDate":"2015-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 0.5-V multi-channel low-noise readout front-end for portable EEG acquisition.\",\"authors\":\"Wen-Yen Huang, Yu-Wei Cheng, Kea-Tiong Tang\",\"doi\":\"10.1109/EMBC.2015.7318492\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article presents a low-noise readout front-end suitable for Electroencephalogram (EEG) acquisition. The chip includes 8-channel fully-differential instrumentation amplifiers, utilizing chopper stabilization technique for reducing the flicker noise, each amplifier with a small Gm-C low-pass filter, a programmable gain amplifier, and a 10-bit successive approximation register (SAR) ADC with a detect logic for DAC switching. The chip is fabricated with the TSMC 90nm CMOS process. The low-noise readout front-end has simulated frequency response from 0.57 Hz to 213 Hz, programmable gain from 54.4 dB to 87.6 dB, integrated input-referred noise of 0.358 μVrms within EEG bandwidth, a noise efficiency factor (NEF) of 2.43, and a power efficiency factor (PEF) of 2.95. The overall system consumes 32.08 μW under 0.5-V supply.\",\"PeriodicalId\":72689,\"journal\":{\"name\":\"Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference\",\"volume\":\"40 1\",\"pages\":\"837-40\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EMBC.2015.7318492\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EMBC.2015.7318492","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.5-V multi-channel low-noise readout front-end for portable EEG acquisition.
This article presents a low-noise readout front-end suitable for Electroencephalogram (EEG) acquisition. The chip includes 8-channel fully-differential instrumentation amplifiers, utilizing chopper stabilization technique for reducing the flicker noise, each amplifier with a small Gm-C low-pass filter, a programmable gain amplifier, and a 10-bit successive approximation register (SAR) ADC with a detect logic for DAC switching. The chip is fabricated with the TSMC 90nm CMOS process. The low-noise readout front-end has simulated frequency response from 0.57 Hz to 213 Hz, programmable gain from 54.4 dB to 87.6 dB, integrated input-referred noise of 0.358 μVrms within EEG bandwidth, a noise efficiency factor (NEF) of 2.43, and a power efficiency factor (PEF) of 2.95. The overall system consumes 32.08 μW under 0.5-V supply.
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