High-Performance Physical-Independent Address-Based Communication Interface for FPGA in Custom Scientific Equipment

Nowadays, in different scientific applications, custom processing systems are particularly suited for Field-Programmable Gate Arrays (FPGA), rather than for Application Specific Integrate Circuits (ASIC). This is mainly due to the added flexibility, simpler design and manufacturing process that FPGA solutions offer, fitting the needs of small-scale custom applications. While the intra-chip data-transfer between the IP-Cores (IPs) that compose the FPGA architecture is relatively easy to implement, the communication system with Temporal Computing (TC) devices is not trivial to build. This contribution focuses on this issue and presents our inter-chip communication system, that possesses the quality of not relying on any specific physical link feature, which allows the use of any type of connection between FPGA and TC devices, as long as it transmits ordered data. Encoding and communication errors are also automatically detected. The system is composed by a software part and a hardware one. The software part is developed in C++, with Python bindings, and provides the read and write methods, to be able to issue the relative commands to an internal standard bus of the FPGA. The hardware part is composed by the sub-modules Packet Transmission Engine (PTE) and Memory Management Engine (MME); the first one being responsible for packets' data framing, integrity check and data multiplexing on the physical link, while the second one executing the read and write operations which were encoded within the packets.