用于时间模式ADC的65纳米CMOS 9位、1.08ps分辨率两步时间-数字转换器

Junjie Kong, S. Henzler, D. Schmitt-Landsiedel, L. Siek
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引用次数: 4

摘要

本文介绍了一种用于时间模式ADC的9位双步时间-数字转换器(TDC)的设计。本文提出的TDC在精细TDC中使用体偏置来获得整个TDC的分辨率,仿真结果为1.08 ps,在555 ps的动态范围内,从START到结果可用的最大转换时间为2.7 ns。建议的TDC在200 MHz时消耗0.667 mW, FoM为0.0065 pJ/转换。DNL和INL分别为- 0.097/0.2 LSB和- 0.12/0.41 LSB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC
This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, the maximum conversion time between START and the availability of results is 2.7 ns. The proposed TDC consumes 0.667 mW at 200 MHz, with a FoM of 0.0065 pJ/conversion. The DNL and INL are simulated to be −0.097/0.2 LSB and −0.12/0.41 LSB respectively.
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