M. Kim, N. Harada, Y. Kikuchi, J. Boemmels, J. Mitard, T. Huynh-Bao, P. Matagne, Z. Tao, W. Li, K. Devriendt, L. Ragnarsson, C. Lorant, F. Sebaai, C. Porret, E. Rosseel, A. Dangol, D. Batuk, G. Martinez-Alanis, J. Geypen, N. Jourdan, A. Sepúlveda, H. Puliyalil, G. Jamieson, M. H. van der Veen, L. Teugels, Z. El-Mekki, E. Altamirano-Sanchez, Y. Li, H. Nakamura, D. Mocuta, F. Masuoka
{"title":"用于垂直6-T SRAM的12 euv层围绕栅极晶体管(SGT):用于超密度逻辑器件的5纳米级技术","authors":"M. Kim, N. Harada, Y. Kikuchi, J. Boemmels, J. Mitard, T. Huynh-Bao, P. Matagne, Z. Tao, W. Li, K. Devriendt, L. Ragnarsson, C. Lorant, F. Sebaai, C. Porret, E. Rosseel, A. Dangol, D. Batuk, G. Martinez-Alanis, J. Geypen, N. Jourdan, A. Sepúlveda, H. Puliyalil, G. Jamieson, M. H. van der Veen, L. Teugels, Z. El-Mekki, E. Altamirano-Sanchez, Y. Li, H. Nakamura, D. Mocuta, F. Masuoka","doi":"10.23919/VLSIT.2019.8776532","DOIUrl":null,"url":null,"abstract":"For the first time, we establish a fabrication process flow of an EUV-era ultra-density 6-surrounding-gate-transistor SRAM with $0.0205\\ \\mu \\text{m}^{2}$ unit cell area and demonstrate nMOS surrounding-gate-transistor function. In this paper, 6-surrounding-gate-transistor SRAM design layout is shown, and the fabrication process flow and key process steps are explained in detail. NMOS functional device characteristics of surrounding-gate-transistor is analyzed.","PeriodicalId":6752,"journal":{"name":"2019 Symposium on VLSI Technology","volume":"75 1","pages":"T198-T199"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices\",\"authors\":\"M. Kim, N. Harada, Y. Kikuchi, J. Boemmels, J. Mitard, T. Huynh-Bao, P. Matagne, Z. Tao, W. Li, K. Devriendt, L. Ragnarsson, C. Lorant, F. Sebaai, C. Porret, E. Rosseel, A. Dangol, D. Batuk, G. Martinez-Alanis, J. Geypen, N. Jourdan, A. Sepúlveda, H. Puliyalil, G. Jamieson, M. H. van der Veen, L. Teugels, Z. El-Mekki, E. Altamirano-Sanchez, Y. Li, H. Nakamura, D. Mocuta, F. Masuoka\",\"doi\":\"10.23919/VLSIT.2019.8776532\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"For the first time, we establish a fabrication process flow of an EUV-era ultra-density 6-surrounding-gate-transistor SRAM with $0.0205\\\\ \\\\mu \\\\text{m}^{2}$ unit cell area and demonstrate nMOS surrounding-gate-transistor function. In this paper, 6-surrounding-gate-transistor SRAM design layout is shown, and the fabrication process flow and key process steps are explained in detail. NMOS functional device characteristics of surrounding-gate-transistor is analyzed.\",\"PeriodicalId\":6752,\"journal\":{\"name\":\"2019 Symposium on VLSI Technology\",\"volume\":\"75 1\",\"pages\":\"T198-T199\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIT.2019.8776532\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIT.2019.8776532","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices
For the first time, we establish a fabrication process flow of an EUV-era ultra-density 6-surrounding-gate-transistor SRAM with $0.0205\ \mu \text{m}^{2}$ unit cell area and demonstrate nMOS surrounding-gate-transistor function. In this paper, 6-surrounding-gate-transistor SRAM design layout is shown, and the fabrication process flow and key process steps are explained in detail. NMOS functional device characteristics of surrounding-gate-transistor is analyzed.
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