Joshua Gunawan, Teresia R. S. Putri, Yashael F. Arthanto, T. Adiono
{"title":"基于递归神经网络和时间反向传播的语音特征情感识别硬件架构","authors":"Joshua Gunawan, Teresia R. S. Putri, Yashael F. Arthanto, T. Adiono","doi":"10.1109/ISPACS48206.2019.8986342","DOIUrl":null,"url":null,"abstract":"Emotion recognition from speech feature is one of the application where the system needs temporal information in order to produce a correct prediction. On the other hand, recurrent neural network has the advantage of retaining temporal information. This paper proposed a hardware architecture design for emotion recognition system using LSTM (Long Short Term Memory) and BPTT (Backpropagation Through Time). For this application, the proposed architecture consists of a two-layer stacked LSTM with 53 cells on the first layer and 8 cells on the second layer. The architecture is implemented and verified using Verilog language and FPGA.","PeriodicalId":6765,"journal":{"name":"2019 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","volume":"12 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Hardware Architecture of Emotion Recognition from Speech Features using Recurrent Neural Network and Backpropagation Through Time\",\"authors\":\"Joshua Gunawan, Teresia R. S. Putri, Yashael F. Arthanto, T. Adiono\",\"doi\":\"10.1109/ISPACS48206.2019.8986342\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Emotion recognition from speech feature is one of the application where the system needs temporal information in order to produce a correct prediction. On the other hand, recurrent neural network has the advantage of retaining temporal information. This paper proposed a hardware architecture design for emotion recognition system using LSTM (Long Short Term Memory) and BPTT (Backpropagation Through Time). For this application, the proposed architecture consists of a two-layer stacked LSTM with 53 cells on the first layer and 8 cells on the second layer. The architecture is implemented and verified using Verilog language and FPGA.\",\"PeriodicalId\":6765,\"journal\":{\"name\":\"2019 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)\",\"volume\":\"12 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPACS48206.2019.8986342\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPACS48206.2019.8986342","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Hardware Architecture of Emotion Recognition from Speech Features using Recurrent Neural Network and Backpropagation Through Time
Emotion recognition from speech feature is one of the application where the system needs temporal information in order to produce a correct prediction. On the other hand, recurrent neural network has the advantage of retaining temporal information. This paper proposed a hardware architecture design for emotion recognition system using LSTM (Long Short Term Memory) and BPTT (Backpropagation Through Time). For this application, the proposed architecture consists of a two-layer stacked LSTM with 53 cells on the first layer and 8 cells on the second layer. The architecture is implemented and verified using Verilog language and FPGA.