一个本地时钟动态逻辑串行/并行乘法器

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044) Pub Date : 2000-05-21 DOI:10.1109/CICC.2000.852713

Gregg N. Hoyer, C. Sechen

{"title":"一个本地时钟动态逻辑串行/并行乘法器","authors":"Gregg N. Hoyer, C. Sechen","doi":"10.1109/CICC.2000.852713","DOIUrl":null,"url":null,"abstract":"Locally-clocked (LC) dynamic logic is an asynchronous circuit technique that uses an event-driven controller to moderate a fine-grained pipeline consisting of latching dynamic logic gates. This paper extends the methodology to include feedback between successive pipeline stages. LC dynamic logic's ability to handle feedback is illustrated with the design of a 660 MHz serial/parallel multiplier implemented in a 1 /spl mu/m, 5 V CMOS process.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"51 1","pages":"481-484"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A locally-clocked dynamic logic serial/parallel multiplier\",\"authors\":\"Gregg N. Hoyer, C. Sechen\",\"doi\":\"10.1109/CICC.2000.852713\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Locally-clocked (LC) dynamic logic is an asynchronous circuit technique that uses an event-driven controller to moderate a fine-grained pipeline consisting of latching dynamic logic gates. This paper extends the methodology to include feedback between successive pipeline stages. LC dynamic logic's ability to handle feedback is illustrated with the design of a 660 MHz serial/parallel multiplier implemented in a 1 /spl mu/m, 5 V CMOS process.\",\"PeriodicalId\":20702,\"journal\":{\"name\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"volume\":\"51 1\",\"pages\":\"481-484\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-05-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2000.852713\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852713","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

本地时钟(LC)动态逻辑是一种异步电路技术，它使用事件驱动控制器来调节由闭锁动态逻辑门组成的细粒度管道。本文扩展了该方法，以包括连续管道阶段之间的反馈。LC动态逻辑处理反馈的能力通过在1 /spl mu/m, 5 V CMOS工艺中实现的660mhz串行/并行乘法器的设计来说明。

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A locally-clocked dynamic logic serial/parallel multiplier

Locally-clocked (LC) dynamic logic is an asynchronous circuit technique that uses an event-driven controller to moderate a fine-grained pipeline consisting of latching dynamic logic gates. This paper extends the methodology to include feedback between successive pipeline stages. LC dynamic logic's ability to handle feedback is illustrated with the design of a 660 MHz serial/parallel multiplier implemented in a 1 /spl mu/m, 5 V CMOS process.

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

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