Energy Efficient and Variability Immune Adder Circuits using Short Gate FinFET INDEP Technique at 10nm technology node

ABSTRACT Due to the continuous scaling of MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) devices over the past few decades, power consumption has increased tremendously. To reduce power dissipation at lower technology nodes, digital logic circuits are designed with modern (FinFET) devices. In this paper, FinFET INDEP (input dependent) technique-based short gate (SG) FinFET Adder circuits are proposed at 10 nm technology node. The performance comparison of INDEP technique-based adder circuits is done with the SG FinFET adder circuits. The analysis of adder circuits is performed first in terms of functional verification (transient characteristics) and finally for different performance parameters such as propagation delay, power dissipation and power delay product (PDP). The proposed FinFET INDEP technique proves as one of the best leakage reduction techniques for FinFET adder circuits at lower technology nodes. To test the reliability of the circuits, Monte Carlo analysis is also performed. The PDP is improved by 16.8% and 13.73% in INDEP SG FinFET half adder(HA) and INDEP SG FinFET full adder(FA) at 10 nm technology, respectively, in comparison with the ones without INDEP technique. The Monte Carlo simulation results with 3σ Gaussian distribution at ±10% process, voltage and temperature variations show the improvement in PDP in case of SG INDEP FinFET FA and SG INDEP FinFET HA circuit in comparison to SG FinFET FA and FinFET HA circuit, respectively. Simulation is performed using HSPICE tool at 10 nm process technology node.