低功耗高密度0.18 /spl mu/m CMOSFET技术栅极延迟的精确评估

Myoung-Kyu Park, H. Lee, M. Jang, Jun-Hyeok Choi, D. Kang, J. Hwang
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引用次数: 0

摘要

在高V/sub / CMOSFET技术中,环形振荡器的栅极延迟随通道宽度(0.72 /spl mu/m-10 /spl mu/m)的变化而变化。推导了包含与通道宽度无关的电容分量的栅极延迟表达式,并与实验结果进行了比较。由于晶体管固有的与通道宽度无关的电容元件,在窄通道宽度区域栅极延迟显著增加。尽管在宽通道宽度下,通道宽度无关电容可以忽略不计,但窄通道宽度(/spl les/1 /spl mu/m)环形振荡器的栅极延迟比5 /spl mu/m通道宽度环形振荡器的栅极延迟增加了20%以上。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Accurate evaluation of gate delay for low-power and high-density 0.18 /spl mu/m CMOSFET technology
The gate delay of ring oscillators in high V/sub T/ CMOSFET technology is characterized with respect to various channel widths (0.72 /spl mu/m-10 /spl mu/m). An expression for gate delay including the channel-width independent capacitance components is derived and compared with experimental results. Substantial increase of gate delay in the narrow channel width region is found due to channel width independent capacitance components which are inherent to transistors. Although the channel width independent capacitance is negligible in wide channel width, gate delay of narrow channel width (/spl les/1 /spl mu/m) ring oscillator increased more than 20% compared with 5 /spl mu/m channel width ring oscillator.
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