Communication techniques for a self-timed massively parallel architecture

A self-timed bit-serial massively parallel architecture is currently being developed to behave correctly independent of intra- and inter-module delays. The self-timed approach abolishes the global clock thus overcoming the limitations associated with global control. These limitations include problems of fixed processing time, clock skew and restricted scalability. This paper introduces self-timed design techniques promoting bit-serial elastic control and data communication in scalable array architectures. A number of different design techniques are introduced and evaluated on a cost, performance basis using the bit-serial Self-Timed Single Instruction Systolic Array (ST-SISA) as a research vehicle.<>