Mohammed Abdulzahra Ahmed Al-Dulaimi, Husam A. Wahhab, Ahmed Abdulhussein Amer
{"title":"基于FPGA平台的音频信号通信数字FIR滤波器设计与实现","authors":"Mohammed Abdulzahra Ahmed Al-Dulaimi, Husam A. Wahhab, Ahmed Abdulhussein Amer","doi":"10.12720/jcm.18.2.89-96","DOIUrl":null,"url":null,"abstract":"Digital Signal Processing (DSP) in telecommunications is widely used for its outstanding performance. Hence, optimal results would be obtained with the sophisticated design and implementation of the digital Finite Impulse Response (FIR) filter. In this paper, the design and implementation of the FIR filter for processing the audio signal are obtained through the Field-Programmable Gate Array (FPGA) platform -Altera DE1 board. The design is divided into three primary blocks, which are the S2P Adapter block, Codec initialization block, as well as FIR filter block, which were then interfaced together; then, every block was compiled and simulated in order to obtain accurate results. The whole system was built to be functional, and finally, the frequency response was obtained. 100% significant accuracy and high quality are examined for implementing the filter in FPGA platform chip board programmed in (VHDL).","PeriodicalId":14832,"journal":{"name":"J. Comput. Mediat. Commun.","volume":"29 1","pages":"89-96"},"PeriodicalIF":0.0000,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Design and Implementation of Communication Digital FIR Filter for Audio Signals on the FPGA Platform\",\"authors\":\"Mohammed Abdulzahra Ahmed Al-Dulaimi, Husam A. Wahhab, Ahmed Abdulhussein Amer\",\"doi\":\"10.12720/jcm.18.2.89-96\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Digital Signal Processing (DSP) in telecommunications is widely used for its outstanding performance. Hence, optimal results would be obtained with the sophisticated design and implementation of the digital Finite Impulse Response (FIR) filter. In this paper, the design and implementation of the FIR filter for processing the audio signal are obtained through the Field-Programmable Gate Array (FPGA) platform -Altera DE1 board. The design is divided into three primary blocks, which are the S2P Adapter block, Codec initialization block, as well as FIR filter block, which were then interfaced together; then, every block was compiled and simulated in order to obtain accurate results. The whole system was built to be functional, and finally, the frequency response was obtained. 100% significant accuracy and high quality are examined for implementing the filter in FPGA platform chip board programmed in (VHDL).\",\"PeriodicalId\":14832,\"journal\":{\"name\":\"J. Comput. Mediat. Commun.\",\"volume\":\"29 1\",\"pages\":\"89-96\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"J. Comput. Mediat. Commun.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.12720/jcm.18.2.89-96\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"J. Comput. Mediat. Commun.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.12720/jcm.18.2.89-96","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and Implementation of Communication Digital FIR Filter for Audio Signals on the FPGA Platform
Digital Signal Processing (DSP) in telecommunications is widely used for its outstanding performance. Hence, optimal results would be obtained with the sophisticated design and implementation of the digital Finite Impulse Response (FIR) filter. In this paper, the design and implementation of the FIR filter for processing the audio signal are obtained through the Field-Programmable Gate Array (FPGA) platform -Altera DE1 board. The design is divided into three primary blocks, which are the S2P Adapter block, Codec initialization block, as well as FIR filter block, which were then interfaced together; then, every block was compiled and simulated in order to obtain accurate results. The whole system was built to be functional, and finally, the frequency response was obtained. 100% significant accuracy and high quality are examined for implementing the filter in FPGA platform chip board programmed in (VHDL).