An All-Digital Clock Generator with Modified Dynamic Frequency Counting Loop and LFSR Dithering

This work presents a modified dynamic frequency counting loop and LFSR dithering for all-digital clock generator. In contrast to fixed clock cycles in conventional design, the modified dynamic frequency counting loop dependents on the states with variable clock cycles. We also applied the LFSR fractional dithering technique to enhance the resolution of multiphase digitally controlled oscillator. A test chip for the proposed all-digital clock generator was fabricated in a standard 0.18µm CMOS technology, and the core area was 0.112mm2. The output frequency had a range of 113MHz~360MHz at 1.8V with RMS jitter 28ps at 359.78MHz/1.8V.