一种新颖的闪存单元和设计优化，用于高密度和低功耗应用

2011 IEEE International Conference of Electron Devices and Solid-State Circuits Pub Date : 2011-12-29 DOI:10.1109/EDSSC.2011.6117733

Huiwei Wu, Shiqiang Qin, Yimao Cai, Poren Tang, Zhan Zhan, Qianqian Huang, Ru Huang

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引用次数: 4

摘要

本文通过二维器件仿真研究了一种基于隧道场效应晶体管(TFET)的新型快闪存储单元。当单元栅长度从180nm扩展到45nm时，该闪存单元的编程/擦除速度加快，编程效率提高，抗穿孔能力增强，具有较强的可扩展性。此外，还研究和讨论了基于tfet的闪速电池的双极性抑制问题。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A novel flash memory cell and design optimization for high density and low power application

A novel flash memory cell based on Tunneling Field Effect Transistor (TFET) is investigated via 2-D device simulation in this paper. The proposed flash memory cell shows improved program/erase speed, increased programming efficiency and super punch-through immunity as the cell gate length scaled from 180nm to 45nm, which indicates that this new structure is with strong scalability. Furthermore, cell design consideration i.e. ambipolar suppression for the TFET-based flash cell are also investigated and discussed.

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来源期刊

2011 IEEE International Conference of Electron Devices and Solid-State Circuits

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