Performance Enhancement of Ge/GaAs Heterostructure Tunnelling Field Effect Transistor

Tunnelling Field Effect Transistor (TFET) is an emerging alternative to Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in device technology as the latter struggles with scaling down effects. But, low on-state current and abrupt doping profile are the limitations of TFET. However, Junctionless Tunnelling Field Effect Transistor (JLTFET) has solved this doping problem by uniformly doping all the regions. A higher tunneling barrier causes the low on-state current, and that is still a limitation of the JLTFET. Our study aims to reduce the tunneling barrier to have a higher on-sate current using Ge/GaAs Heterostructure Junctionless Tunnelling Field Effect Transistor (H-JLTFET) and enhance the overall performance of this H-JLTFET by analyzing different device parameters, such as channel thickness, oxide thickness, and doping concentration. The Non-Local Band to Band Tunnelling (BTBT) model was employed to achieve a realistic tunneling mechanism in our device using TCAD. Our proposed device provides a high on-state current of 7.68e-5 A/um, a low off-state current of 7.4e-17 A/um, nearly an ideal subthreshold swing of 5.73 mV/decade. Finally, this work concludes with a comparative study between our optimized device and other published similar TFET. The analysis shows that our device provides a significant improvement in performance, which could be very promising for the emerging low-power, high-speed VLSI technology.