Performance analysis and optimization of 10 nm TG N- and P-channel SOI FinFETs for circuit applications

This paper analyses the electrical characteristics of 10 nm tri-gate (TG) N- and P-channel silicon-on-insulator (SOI) FinFETs with hafnium oxide gate dielectric. The analysis has been performed through simulations by using Silvaco ATLAS TCAD with the Bohm quantum potential (BQP) algorithm. The influence of the geometrical parameters on the threshold voltage VTH, the subthreshold swing (SS), the transconductance and the on/off current ratio, ION/IOFF, is investigated. The two structures have been optimized for CMOS inverter implementation. The simulation results show that the N-FinFET and the P-FinFET can reach a minimum SS value with Fin heights of 15 nm and 9 nm, respectively. In addition, low threshold voltages of 0.61 V and 0.27 V for N- and P-channel SOI FinFETs, respectively, are obtained at a Fin width of 7 nm.