影响以太网延迟的硬件/软件实现因素

Tomas P. Correa, L. Almeida, E. B. Peña
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引用次数: 2

摘要

最小周期时间是比较实时以太网协议的常用性能指标。最小周期时间虽然达到了它的目的,但它排除了发送和接收节点内部的延迟,因此不足以估计端到端延迟。在这项工作中,我们描述了在片上系统中以太网节点的一些实现可能性,并给出了从应用层发送/接收数据包的延迟测量。我们在软件中选择不同的点来进行测量,因此结果涵盖了更多的用例。我们发现以太网Lite媒体访问控制器(MAC)比硬MAC (GEM)和轻量级IP堆栈快,增加不到2.2 μs。最后,我们展示了硬件加速器如何将高优先级数据包的延迟减少1.4 μs。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Hardware/Software Implementation Factors Influencing Ethernet Latency
Minimum Cycle Time is a common performance indicator adopted to compare Real-Time Ethernet protocols. Though serving its purpose, Minimum Cycle Time excludes the delays inside the sending and receiving nodes, so it is insufficient to estimate the end-to-end latency. In this work, we describe some implementation possibilities of an Ethernet node in a System-on-Chip and present measurements of the delay to send/receive packets from/to the application layer. We chose different points in the software to make the measurement, so the results cover more use-cases. We found the Ethernet Lite Media Access Controller (MAC) to be faster than the hard MAC (GEM) and the Lightweight IP stack to add less than 2.2 μs. Finally, we show how a hardware accelerator can reduce the delay of high-priority packets by 1.4 μs.
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