{"title":"一种用于卫星电路的turbo/MAP解码器","authors":"S. Pietrobon","doi":"10.1109/ICICS.1997.647132","DOIUrl":null,"url":null,"abstract":"The implementation and performance of a turbo/MAP decoder is described. A serial block MAP decoder operating in the logarithm domain is used to obtain a very high performance turbo decoder. Programmable gate arrays and EPROMs allow the decoder to be programmed for almost any code from 4 to 512 states, rate 1/3 to rate 1/7 (higher rates are achieved with puncturing), and interleaver block sizes to 65,536 bits. Seven decoding stages were implemented in parallel. For rate 1/3 and 1/7 16 state codes with an interleaver size of 65,536 bits and operating at up to 356 kbit/s the codec achieved an E/sub b//N/sub 0/ of 0.32 and -0.30 dB, respectively for a BER of 10/sup -5/. BERs down to 10/sup -7/ were also achieved for a small increase in E/sub b//N/sub 0/.","PeriodicalId":71361,"journal":{"name":"信息通信技术","volume":"362 1","pages":"427-431 vol.1"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A turbo/MAP decoder for use in satellite circuits\",\"authors\":\"S. Pietrobon\",\"doi\":\"10.1109/ICICS.1997.647132\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The implementation and performance of a turbo/MAP decoder is described. A serial block MAP decoder operating in the logarithm domain is used to obtain a very high performance turbo decoder. Programmable gate arrays and EPROMs allow the decoder to be programmed for almost any code from 4 to 512 states, rate 1/3 to rate 1/7 (higher rates are achieved with puncturing), and interleaver block sizes to 65,536 bits. Seven decoding stages were implemented in parallel. For rate 1/3 and 1/7 16 state codes with an interleaver size of 65,536 bits and operating at up to 356 kbit/s the codec achieved an E/sub b//N/sub 0/ of 0.32 and -0.30 dB, respectively for a BER of 10/sup -5/. BERs down to 10/sup -7/ were also achieved for a small increase in E/sub b//N/sub 0/.\",\"PeriodicalId\":71361,\"journal\":{\"name\":\"信息通信技术\",\"volume\":\"362 1\",\"pages\":\"427-431 vol.1\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"信息通信技术\",\"FirstCategoryId\":\"1093\",\"ListUrlMain\":\"https://doi.org/10.1109/ICICS.1997.647132\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"信息通信技术","FirstCategoryId":"1093","ListUrlMain":"https://doi.org/10.1109/ICICS.1997.647132","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The implementation and performance of a turbo/MAP decoder is described. A serial block MAP decoder operating in the logarithm domain is used to obtain a very high performance turbo decoder. Programmable gate arrays and EPROMs allow the decoder to be programmed for almost any code from 4 to 512 states, rate 1/3 to rate 1/7 (higher rates are achieved with puncturing), and interleaver block sizes to 65,536 bits. Seven decoding stages were implemented in parallel. For rate 1/3 and 1/7 16 state codes with an interleaver size of 65,536 bits and operating at up to 356 kbit/s the codec achieved an E/sub b//N/sub 0/ of 0.32 and -0.30 dB, respectively for a BER of 10/sup -5/. BERs down to 10/sup -7/ were also achieved for a small increase in E/sub b//N/sub 0/.
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