{"title":"一种220pJ/像素/帧CMOS图像传感器，具有部分沉降读出结构","authors":"Suyao Ji, Jing Pu, Byongchan Lim, M. Horowitz","doi":"10.1109/VLSIC.2016.7573545","DOIUrl":null,"url":null,"abstract":"To reduce power consumption in a CMOS imager readout path, we use partial settling of the column values into a SAR-ADC, creating a 320H×240V prototype sensor with two column-shared 10-bit ADCs, which consumes 2.2mW at 130 fps. The measured INL and DNL with a third order correction of partial settling behavior is +1.855LSB/-1.855LSB and +0.337LSB/-0.179LSB, respectively. The input referred readout noise is 5e- with a conversion gain of 90uV/e-.","PeriodicalId":6512,"journal":{"name":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","volume":"9 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A 220pJ/pixel/frame CMOS image sensor with partial settling readout architecture\",\"authors\":\"Suyao Ji, Jing Pu, Byongchan Lim, M. Horowitz\",\"doi\":\"10.1109/VLSIC.2016.7573545\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"To reduce power consumption in a CMOS imager readout path, we use partial settling of the column values into a SAR-ADC, creating a 320H×240V prototype sensor with two column-shared 10-bit ADCs, which consumes 2.2mW at 130 fps. The measured INL and DNL with a third order correction of partial settling behavior is +1.855LSB/-1.855LSB and +0.337LSB/-0.179LSB, respectively. The input referred readout noise is 5e- with a conversion gain of 90uV/e-.\",\"PeriodicalId\":6512,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"volume\":\"9 1\",\"pages\":\"1-2\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2016.7573545\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2016.7573545","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 220pJ/pixel/frame CMOS image sensor with partial settling readout architecture
To reduce power consumption in a CMOS imager readout path, we use partial settling of the column values into a SAR-ADC, creating a 320H×240V prototype sensor with two column-shared 10-bit ADCs, which consumes 2.2mW at 130 fps. The measured INL and DNL with a third order correction of partial settling behavior is +1.855LSB/-1.855LSB and +0.337LSB/-0.179LSB, respectively. The input referred readout noise is 5e- with a conversion gain of 90uV/e-.
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