{"title":"具有周期性时变系数的无乘法器IIR滤波器实现","authors":"S. Tantaratana","doi":"10.1109/APCAS.1996.569227","DOIUrl":null,"url":null,"abstract":"In this paper, we extend the periodically time-varying (PTV) filter realization, which was proposed for the FIR filter, to be used for IIR filters. The realization consists of ternary ({0, /spl plusmn/1}) or quinary ({0, /spl plusmn/1, /spl plusmn/2}) PTV coefficients with simple input and output units. The coefficients as well as the input and output units require no hardware multiplier. This simplifies the layout for VLSI implementation and increases the processing speed.","PeriodicalId":20507,"journal":{"name":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","volume":"10 1","pages":"93-96"},"PeriodicalIF":0.0000,"publicationDate":"1996-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Multiplier-free IIR filter realizations with periodically time-varying coefficients\",\"authors\":\"S. Tantaratana\",\"doi\":\"10.1109/APCAS.1996.569227\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we extend the periodically time-varying (PTV) filter realization, which was proposed for the FIR filter, to be used for IIR filters. The realization consists of ternary ({0, /spl plusmn/1}) or quinary ({0, /spl plusmn/1, /spl plusmn/2}) PTV coefficients with simple input and output units. The coefficients as well as the input and output units require no hardware multiplier. This simplifies the layout for VLSI implementation and increases the processing speed.\",\"PeriodicalId\":20507,\"journal\":{\"name\":\"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems\",\"volume\":\"10 1\",\"pages\":\"93-96\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-11-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCAS.1996.569227\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCAS.1996.569227","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Multiplier-free IIR filter realizations with periodically time-varying coefficients
In this paper, we extend the periodically time-varying (PTV) filter realization, which was proposed for the FIR filter, to be used for IIR filters. The realization consists of ternary ({0, /spl plusmn/1}) or quinary ({0, /spl plusmn/1, /spl plusmn/2}) PTV coefficients with simple input and output units. The coefficients as well as the input and output units require no hardware multiplier. This simplifies the layout for VLSI implementation and increases the processing speed.
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