14nm三栅极CMOS中4fJ/bit延迟硬化物理不可克隆电路

2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits) Pub Date : 2016-06-15 DOI:10.1109/VLSIC.2016.7573554

S. Mathew, Sudhir K. Satpathy, Vikram B. Suresh, M. Anders, Himanshu Kaul, A. Agarwal, S. Hsu, Gregory K. Chen, R. Krishnamurthy, V. De

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引用次数: 8

摘要

采用14nm三栅极CMOS制造了一个1024位延迟硬化物理不可克隆功能(PUF)阵列，目标是在片上安全生成全熵128位密钥。差分时钟延迟注入、不稳定比特的选择性不稳定和基于时间多数投票(TMV)的窗口化使刻录后误码率提高1.7倍，黑比特引起的误码率降低50%，最坏情况误码率为1.46%。不稳定PUF比特的频谱分析显示在500MHz以下有显著的1/f噪声影响。采用写反馈的现场老化技术可将钻头稳定性提高48%。

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A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS

A 1024-bit delay-hardened physically unclonable function (PUF) array is fabricated in 14nm tri-gate CMOS, targeted for on-die secure generation of a full-entropy 128bit key. Differential clock delay injection, selective destabilization of unstable bits and temporal-majority-voting (TMV) based winnowing enable 1.7× higher post-burn-in BER improvement, 50% reduction in dark-bit induced bit-errors and worst-case BER of 1.46%. Spectral analysis of unstable PUF bits show significant 1/f noise impacts below 500MHz. In-situ field aging with write feedback improves bit stability by up to 48%.

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2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits)

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