{"title":"考虑端口间公平性的低延迟调度算法","authors":"Hirotada Kawakami, Koichi Asatani","doi":"10.1002/ecja.20313","DOIUrl":null,"url":null,"abstract":"<p>A Virtual Output Queuing (VOQ) input buffer type switch provided with a buffer in each input port is proposed in this paper as an input buffer type switch that avoids Head-of-Line (HoL) blocking. A scheduling algorithm for a multiple VOQ input buffer type switch is also proposed. As a representative algorithm we use a Two-Dimensional Round Robin (2DRR) scheduling algorithm that achieves low-delay and has iSLIP to avoid starvation as well as high fairness between ports. This paper also proposes a layered scheduling algorithm for a VOQ input buffer type switch with an objective of fairness between ports and switching with lower delay. The frequency of packets not being output is reduced regardless of whether an output port is empty by using up patterns of all I/O pairs in <i>N</i> input <i>N</i> output switches. The <i>N</i> input <i>N</i> output switching is divided into smaller units. Fairness between the units is achieved by successively shifting the order of priority of each unit that will be switched. Simulations were used to evaluate the effectiveness of the proposed scheduling algorithm. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 1, 90(6): 43–52, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecja.20313</p>","PeriodicalId":100405,"journal":{"name":"Electronics and Communications in Japan (Part I: Communications)","volume":"90 6","pages":"43-52"},"PeriodicalIF":0.0000,"publicationDate":"2007-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1002/ecja.20313","citationCount":"0","resultStr":"{\"title\":\"Low-delay scheduling algorithm that considers fairness between ports\",\"authors\":\"Hirotada Kawakami, Koichi Asatani\",\"doi\":\"10.1002/ecja.20313\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<p>A Virtual Output Queuing (VOQ) input buffer type switch provided with a buffer in each input port is proposed in this paper as an input buffer type switch that avoids Head-of-Line (HoL) blocking. A scheduling algorithm for a multiple VOQ input buffer type switch is also proposed. As a representative algorithm we use a Two-Dimensional Round Robin (2DRR) scheduling algorithm that achieves low-delay and has iSLIP to avoid starvation as well as high fairness between ports. This paper also proposes a layered scheduling algorithm for a VOQ input buffer type switch with an objective of fairness between ports and switching with lower delay. The frequency of packets not being output is reduced regardless of whether an output port is empty by using up patterns of all I/O pairs in <i>N</i> input <i>N</i> output switches. The <i>N</i> input <i>N</i> output switching is divided into smaller units. Fairness between the units is achieved by successively shifting the order of priority of each unit that will be switched. Simulations were used to evaluate the effectiveness of the proposed scheduling algorithm. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 1, 90(6): 43–52, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecja.20313</p>\",\"PeriodicalId\":100405,\"journal\":{\"name\":\"Electronics and Communications in Japan (Part I: Communications)\",\"volume\":\"90 6\",\"pages\":\"43-52\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-02-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://sci-hub-pdf.com/10.1002/ecja.20313\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Electronics and Communications in Japan (Part I: Communications)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://onlinelibrary.wiley.com/doi/10.1002/ecja.20313\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electronics and Communications in Japan (Part I: Communications)","FirstCategoryId":"1085","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1002/ecja.20313","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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