一个0.6-3.0GHz 65nm CMOS无线电接收机与ΔΣ-based A/ d转换通道选择滤波器

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC) Pub Date : 2015-11-02 DOI:10.1109/ESSCIRC.2015.7313886

Anders Nejdel, Xiaodong Liu, Mattias Palm, Lars Sundström, Markus Törmänen, H. Sjöland, P. Andreani

{"title":"一个0.6-3.0GHz 65nm CMOS无线电接收机与ΔΣ-based A/ d转换通道选择滤波器","authors":"Anders Nejdel, Xiaodong Liu, Mattias Palm, Lars Sundström, Markus Törmänen, H. Sjöland, P. Andreani","doi":"10.1109/ESSCIRC.2015.7313886","DOIUrl":null,"url":null,"abstract":"We present a wideband quadrature radio receiver employing ΔΣ-based A/D-converting channel-select filters (AD-CSFs). The output of the quadrature passive mixer is directly connected to the input of the ADCSFs, which incorporate the functionalities of both channel selection and data conversion in a single power-optimized block. The 65nm CMOS receiver has a frequency range of 0.6-3.0 GHz and can be programmed to support the 2xLTE20, LTE20, and LTE10 bandwidths. The receiver noise figure varies from 2.4 to 3.5 dB. In 2xLTE20 mode, the current consumption is between 33mA at 0.6 GHz and 44mA at 3.0 GHz, including 10-21mA for LO generation and distribution, supplied from 1.2 V. The SNDR is 47-51dB at an LO frequency of 1.8 GHz.","PeriodicalId":11845,"journal":{"name":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2015-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A 0.6–3.0GHz 65nm CMOS radio receiver with ΔΣ-based A/D-converting channel-select filters\",\"authors\":\"Anders Nejdel, Xiaodong Liu, Mattias Palm, Lars Sundström, Markus Törmänen, H. Sjöland, P. Andreani\",\"doi\":\"10.1109/ESSCIRC.2015.7313886\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a wideband quadrature radio receiver employing ΔΣ-based A/D-converting channel-select filters (AD-CSFs). The output of the quadrature passive mixer is directly connected to the input of the ADCSFs, which incorporate the functionalities of both channel selection and data conversion in a single power-optimized block. The 65nm CMOS receiver has a frequency range of 0.6-3.0 GHz and can be programmed to support the 2xLTE20, LTE20, and LTE10 bandwidths. The receiver noise figure varies from 2.4 to 3.5 dB. In 2xLTE20 mode, the current consumption is between 33mA at 0.6 GHz and 44mA at 3.0 GHz, including 10-21mA for LO generation and distribution, supplied from 1.2 V. The SNDR is 47-51dB at an LO frequency of 1.8 GHz.\",\"PeriodicalId\":11845,\"journal\":{\"name\":\"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2015.7313886\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2015.7313886","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 8

摘要

我们提出了一种采用ΔΣ-based a / d转换信道选择滤波器(AD-CSFs)的宽带正交无线电接收机。正交无源混频器的输出直接连接到adcsf的输入，adcsf在单个功率优化块中包含通道选择和数据转换的功能。65nm CMOS接收器的频率范围为0.6-3.0 GHz，可以编程以支持2xLTE20, LTE20和LTE10带宽。接收机噪声系数从2.4到3.5 dB不等。在2xLTE20模式下，电流消耗在0.6 GHz时的33mA和3.0 GHz时的44mA之间，包括LO产生和分配的10-21mA，由1.2 V供电。在本端频率为1.8 GHz时，SNDR为47-51dB。

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A 0.6–3.0GHz 65nm CMOS radio receiver with ΔΣ-based A/D-converting channel-select filters

We present a wideband quadrature radio receiver employing ΔΣ-based A/D-converting channel-select filters (AD-CSFs). The output of the quadrature passive mixer is directly connected to the input of the ADCSFs, which incorporate the functionalities of both channel selection and data conversion in a single power-optimized block. The 65nm CMOS receiver has a frequency range of 0.6-3.0 GHz and can be programmed to support the 2xLTE20, LTE20, and LTE10 bandwidths. The receiver noise figure varies from 2.4 to 3.5 dB. In 2xLTE20 mode, the current consumption is between 33mA at 0.6 GHz and 44mA at 3.0 GHz, including 10-21mA for LO generation and distribution, supplied from 1.2 V. The SNDR is 47-51dB at an LO frequency of 1.8 GHz.

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ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC)

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