C. Recoquillon, J. Bégueret, Y. Deval, G. Montignac, A. Baudry
{"title":"一个4 Gsps, 2-4 GHz输入带宽，3位闪存A/D转换器","authors":"C. Recoquillon, J. Bégueret, Y. Deval, G. Montignac, A. Baudry","doi":"10.1109/ICECS.2004.1399665","DOIUrl":null,"url":null,"abstract":"This paper presents the digitizer developed for the second phase of the ALMA (Atacama Large Millimeter Array) project. This ASIC is a monolithic A/D converter implemented in a BiCMOS 0.25 /spl mu/m. SiGe process from STMicroelectronics. The main features of the ADC are a 3 bit resolution (8 quantization levels), an input bandwidth from 2 to 4 GHz with 4 GHz sample rate. The design architecture of this digitizer is based on a conventional flash analog to digital converter structure. The comparator outputs are coded by a FDL encoder with a 3-bit Gray code. The measurement results, depicted at the end of this paper, show that the converter is operational for clock rates up to 5.5 GHz. The overall chip dissipates 1.4 W under 2.5 V and the die area is 9 mm/sup 2/.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"A 4 Gsps, 2-4 GHz input bandwidth, 3-bits flash A/D converter\",\"authors\":\"C. Recoquillon, J. Bégueret, Y. Deval, G. Montignac, A. Baudry\",\"doi\":\"10.1109/ICECS.2004.1399665\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the digitizer developed for the second phase of the ALMA (Atacama Large Millimeter Array) project. This ASIC is a monolithic A/D converter implemented in a BiCMOS 0.25 /spl mu/m. SiGe process from STMicroelectronics. The main features of the ADC are a 3 bit resolution (8 quantization levels), an input bandwidth from 2 to 4 GHz with 4 GHz sample rate. The design architecture of this digitizer is based on a conventional flash analog to digital converter structure. The comparator outputs are coded by a FDL encoder with a 3-bit Gray code. The measurement results, depicted at the end of this paper, show that the converter is operational for clock rates up to 5.5 GHz. The overall chip dissipates 1.4 W under 2.5 V and the die area is 9 mm/sup 2/.\",\"PeriodicalId\":38467,\"journal\":{\"name\":\"Giornale di Storia Costituzionale\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-12-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Giornale di Storia Costituzionale\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2004.1399665\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"Arts and Humanities\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Giornale di Storia Costituzionale","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2004.1399665","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"Arts and Humanities","Score":null,"Total":0}
This paper presents the digitizer developed for the second phase of the ALMA (Atacama Large Millimeter Array) project. This ASIC is a monolithic A/D converter implemented in a BiCMOS 0.25 /spl mu/m. SiGe process from STMicroelectronics. The main features of the ADC are a 3 bit resolution (8 quantization levels), an input bandwidth from 2 to 4 GHz with 4 GHz sample rate. The design architecture of this digitizer is based on a conventional flash analog to digital converter structure. The comparator outputs are coded by a FDL encoder with a 3-bit Gray code. The measurement results, depicted at the end of this paper, show that the converter is operational for clock rates up to 5.5 GHz. The overall chip dissipates 1.4 W under 2.5 V and the die area is 9 mm/sup 2/.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
