{"title":"一种40nm CMOS 12b 200MS/s单放大器双残差流水线sar ADC","authors":"M. Seo, Ye-Dam Kim, Jae-Hyun Chung, S. Ryu","doi":"10.23919/VLSIC.2019.8778005","DOIUrl":null,"url":null,"abstract":"This work proposes a dual-residue pipelined-SAR ADC that generates two residue signals from a single amplifier, which eliminates the need for gain-matching calibration. A capacitive interpolating SAR conversion technique is also proposed for the second stage for power efficiency. A prototype ADC fabricated in a 40nm CMOS occupies an active area of 0.026 mm2 and achieves an SNDR of 62.1 dB at Nyquist and 67.1 dB SFDR under a 0.9 V supply.","PeriodicalId":6707,"journal":{"name":"2019 Symposium on VLSI Circuits","volume":"11 1","pages":"C72-C73"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC\",\"authors\":\"M. Seo, Ye-Dam Kim, Jae-Hyun Chung, S. Ryu\",\"doi\":\"10.23919/VLSIC.2019.8778005\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work proposes a dual-residue pipelined-SAR ADC that generates two residue signals from a single amplifier, which eliminates the need for gain-matching calibration. A capacitive interpolating SAR conversion technique is also proposed for the second stage for power efficiency. A prototype ADC fabricated in a 40nm CMOS occupies an active area of 0.026 mm2 and achieves an SNDR of 62.1 dB at Nyquist and 67.1 dB SFDR under a 0.9 V supply.\",\"PeriodicalId\":6707,\"journal\":{\"name\":\"2019 Symposium on VLSI Circuits\",\"volume\":\"11 1\",\"pages\":\"C72-C73\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-06-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.23919/VLSIC.2019.8778005\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/VLSIC.2019.8778005","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC
This work proposes a dual-residue pipelined-SAR ADC that generates two residue signals from a single amplifier, which eliminates the need for gain-matching calibration. A capacitive interpolating SAR conversion technique is also proposed for the second stage for power efficiency. A prototype ADC fabricated in a 40nm CMOS occupies an active area of 0.026 mm2 and achieves an SNDR of 62.1 dB at Nyquist and 67.1 dB SFDR under a 0.9 V supply.
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