Area Efficient Hybrid Parallel Prefix Adders

Addition is a timing critical operation in almost all modern processing units. The performance parameters such as the implementation area, the adder latency and the power dissipation decide the choice of adders for different applications. Hence, there is an extensive research attention towards designing higher speed and less complex adder architectures with lower power dissipation. Among the several adder topologies available, parallel-prefix adders are the most frequently employed as they offer many design choices for achieving area/power/delay efficiency and they also provide optimization of the trade-offs. This paper discusses the design and implementation of area-power optimized hybrid parallel-prefix Ling adder. The hybrid adder topology employed in this work uses Ladner-Fischer approach for even-indexed and Kogge-Stone structure for odd-indexed bits. The independent computation of carries for odd and even bits, directly leads to the reduction of fan-out of the prefix tree and thereby a reduced delay. The area efficiency is achieved by the computation of the real carries using modified Ling's equations. The proposed adders are implemented with word size of 16 bit and 32 bit based on modified Ling equations using 0.18 μm CMOS technology. The synthesis results reveal that the proposed adders could achieve up to 24% and 35% saving of area-power product and power-delay product respectively, over the adders based on conventional Ling equations.