用于SHA-3候选算法性能评估的原型平台

Kazuyuki Kobayashi, Jun Ikegami, K. Sakiyama, K. Ohta, Miroslav Knezevic, Ünal Koçabas, Junfeng Fan, I. Verbauwhede, Eric Xu Guo, Shin'ichiro Matsuo, Sinan Huang, L. Nazhandali, Akashi Satoh
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引用次数: 25

摘要

SHA-3 NIST竞赛的目标是从多个竞争的候选算法中选择一种用于加密散列的标准算法。选定的获胜者必须在广泛的目标平台(包括软件和硬件)上具有足够的加密特性和良好的实现特性。硬件的性能评估尤其具有挑战性,因为设计空间大,目标技术范围广,优化标准众多。我们描述了三个研究小组使用通用原型平台评估SHA-3候选方案的努力。使用SASEBO-GII FPGA板作为起点,我们评估了其余14个SHA-3候选器件在面积、吞吐量和功耗方面的性能。我们的方法为SHA-3候选者定义了一个标准测试工具,包括SASEBO测试板上SHA-3模块的接口规范。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Prototyping platform for performance evaluation of SHA-3 candidates
The objective of the SHA-3 NIST competition is to select, from multiple competing candidates, a standard algorithm for cryptographic hashing. The selected winner must have adequate cryptographic properties and good implementation characteristics over a wide range of target platforms, including both software and hardware. Performance evaluation in hardware is particularly challenging because of the large design space, wide range of target technologies, and multitude of optimization criteria. We describe the efforts of three research groups to evaluate SHA-3 candidates using a common prototyping platform. Using a SASEBO-GII FPGA board as a starting point, we evaluate the performance of the 14 remaining SHA-3 candidates with respect to area, throughput, and power consumption. Our approach defines a standard testing harness for SHA-3 candidates, including the interface specifications for the SHA-3 module on the SASEBO testing board.
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