一种实验性并行微处理器系统

C.Dwayne Ethridge, James W Moore, Vito A Trujillo
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引用次数: 0

摘要

洛斯阿拉莫斯国家实验室的计算部门设计并正在建造一个并行微处理器系统(PμPS),作为评估大规模科学代码并行处理的研究工具。PμPS是由32个内存元件组成的20个处理元件的正交阵列组成的实验架构,建立了一个紧密耦合的共享内存(16mbyte)机器。硬件集成了非常大规模的集成组件,如16位微处理器、浮点协处理器和动态随机存取存储器。该设计用可编程阵列逻辑、逻辑顺序器和逻辑阵列取代传统的中等规模集成或小规模集成电路。这个实验系统只是实验室计算部门正在进行的并行处理研究的一个组成部分,它将能够直接比较各种多处理器架构下算法的加速。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An experimental parallel microprocessor system

The Computing Division at the Los Alamos National Laboratory has designed and is building a parallel microprocessor system (PμPS) to serve as a research tool for evaluating parallel processing of large-scale scientific codes. The PμPS is an experimental architecture consisting of an orthogonal array of 20 processing elements by 32 memory elements, establishing a tightly coupled shared memory (16-Mbyte) machine. The hardware incorporates very-large-scale integration components, such as 16-bit microprocessors, floating-point co-processors and dynamic random access memories. The design replaces the conventional medium-scale integration or small-scale integration circuitry with programmable array logic, logic sequencers and logic arrays. This experimental system, which is only one element of the parallel processing research being done by the Laboratory's Computing Division, will enable direct comparisons of speed-ups of algorithms for a variety of multiprocessor architectures.

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