6-T XOR-XNOR单元全加法器设计及性能分析

IF 0.6 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

Facta Universitatis-Series Electronics and Energetics Pub Date : 2022-01-01 DOI:10.2298/fuee2202187r

R. Srinivasa, M. Aditya, R. Karthik, CH. Manisai, S. Tharun, Girija Sravani

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引用次数: 0

摘要

本文对一种高速、低功耗的6-T XOR-XNOR电路进行了设计与仿真。同时，利用异或异或电路、求和和进位，设计并仿真了由16个晶体管组成的1位混合式全加法器，以提高其面积和速度性能。其性能分别与20个和18个晶体管的全加法器设计进行了比较。采用180 nm和90nm的CMOS技术，在Microwind工具中对所提出的电路进行了仿真，测试了电路的性能。所提出的电路的性能是根据功率、延迟和PDP(功率延迟积)来测量的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design and performance analysis of full adder using 6-T XOR-XNOR cell

In this paper, the design and simulation of a high-speed, low power 6-T XOR-XNOR circuit is carried out. Also, the design and simulation of 1-bit hybrid full adder (consisting of 16 transistors) using XOR-XNOR circuit, sum, and carry, is performed to improve the area and speed performance. Its performance is being compared with full adder designs with 20 and 18 transistors, respectively. The performance of the proposed circuits is measured by simulating them in Microwind tool using 180 and 90nm CMOS technology. The performance of the proposed circuit is measured in terms of power, delay, and PDP (Power Delay Product).

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来源期刊

Facta Universitatis-Series Electronics and Energetics ENGINEERING, ELECTRICAL & ELECTRONIC-

自引率

16.70%

发文量

审稿时长

20 weeks